The present invention relates to switching technology in computer networks. More particularly it refers to a method and system for switching information packets through a multiple (m) input, multiple (n) output device.
During the last years the data traffic through electronic networks has increased remarkably. This tendency was strongly triggered by the general acceptance and frequent use of the Internet by private persons and enterprises.
In general, the data is transferred in packets from the start node to the end node of a respective data transmission. Between start node and end node in general, a plurality of nodes are used during packet transmission at which a packet is routed in one—when monocast—and into several directions—when multicast transmission—in order to arrive finally at the end node.
At any intermediate node a kind of switching device having a number of m input ports and a number of n output ports routs the packets according to the intended target node. The physical line onto which this is done is called a link. Thus, in a network nodes are connected by one or more links which are often full duplex links which allow simultaneous communications in both directions. Both ends of each link are terminated by a ‘link-circuit’ which is also called a port.
A switch is thus a key component of the entire network. It is called non-blocking when it can simultaneously interconnect several pairs of selected links. It is also called a cut-through switch when it can begin re-transmitting (i.e., forwarding) data packets well before the complete packet has been received. In European patent application EP 0404423 a respective disclosure can be found related to the specific prior art network switches. This disclosure is incorporated herein by reference. In order to increase the throughput through such switching devices a modern switching device supports the so-called link paralleling mode (LP mode) in which temporarily several ports, for example up to 4 ports build one logical port. This is done in order to virtually and temporarily increase the bandwidth of a selected link.
Further, a modern switch supports more then one switching priorities, further referred to herein as lanes.
A disadvantage of switches supporting link paralleling mode and multiple lanes is their latency, i.e. the time between the packet arrival and the packet departure.
The problem concerned with the present invention is now in more detail the following: The basic principle of any packet switch network is to route incoming packets from any of the input ports n to one or more of the m output ports while maintaining the sequence of the packet flow. Thus, when a data transmission comprises 47 single packets, for example, the sequence of them must be tracked precisely in order to being able to built up the desired data at the target node computer in the same way as it was sent from the originating computer.
In prior art this control job is done by so-called ‘linked lists’ which keep precisely track of the packet sequence. This is done in prior art by an address manager which provides to each incoming packet an address at which this packet is stored in memory. This, however, is only done when the traffic amount exceeds a certain limit and a data packet must be buffered temporarily before it can be sent out to the desired output port. The basic principle of the linked list concept is to store the address location of the subsequent packet with the current address location. This concept has, however some disadvantages, as reveals next below.
When trying to increase the throughput performance by using a higher performing server computer processor having a higher clock rate than that one used before, the linked list approach represents a significant obstacle for the expected throughput increase because the walking through the linked list required for routing the complete packet sequences requires in turn a read process of a packet, each.
A further disadvantage of the linked list approach is that a whole packet sequence must be sent a second time when a single address control bit used in the linklist addressing scheme has lost the correct value, may be generated by a hardware error. Then, the sequence is interrupted and the packet subsequent to the current packet can not be found anymore in the switch memory.
Thus, it would be desirable to have a switching device which is able to increase the throughput with increasing clockrate.